An area/performance trade-off analysis of a GF(2m) multiplier architecture for elliptic curve cryptography
نویسندگان
چکیده
A hardware architecture for GF(2 m ) multiplication and its evaluation in a hardware architecture for elliptic curve scalar multiplication is presented. The architecture is a parametrizable digit-serial implementation for any field order m. Area/performance trade-off results of the hardware implementation of the multiplier in an FPGA are presented and discussed.
منابع مشابه
An area/performance trade-off analysis of a GF(2) multiplier architecture for elliptic curve cryptography
A hardware architecture for GF(2 m) multiplication and its evaluation in a hardware architecture for elliptic curve scalar multiplication is presented. The architecture is a parameter-izable digit-serial implementation for any field order m. Area/performance trade-off results of the hardware implementation of the multiplier in an FPGA are presented and discussed. Finite fields like the binary G...
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عنوان ژورنال:
- Computers & Electrical Engineering
دوره 35 شماره
صفحات -
تاریخ انتشار 2009